1. Field of the Invention
This application claims priority based on Japanese Patent Application No. 2006-351203 filed in Japan on Dec. 27, 2006, the disclosure of which is incorporated herein by reference.
The present invention relates to a clock signal generating device and an analog-digital conversion device including the clock signal generating device.
2. Description of the Related Art
In recent years, a technique for A/D conversion with high precision and at high speed in a communication filed such as a wireless LAN or a imaging technique such as a digital TV has been required. Among techniques to speed up the A/D conversion, there is an interleaved constitution in which A/D converters of both A/B channels are processed in parallel in a time-division manner, and a double sampling technique in which an operation amplifier is commoditized among the interleaves, as described in “Low-Power Pipeline ADC for Wireless LANs”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, August 2004. Although high-speed A/D conversion is realized by the interleaved constitution, the problem is that when the sampling timing difference is generated between both A/B channels, the characteristics are degraded because of the timing difference.
The A/D converter switches between a sampling period and a holding period according to a clock signal. Especially, the A/D conversion device having the interleaved constitution processes the A/D converters of both A/B channels in parallel in the time-division manner, according to two mutually inverted (phase difference is 180°) clock signals. Conventionally, the two mutually inverted clock signals are provided by a clock signal generating device 50 as shown in FIG. 6, for example.
FIG. 6 is a circuit diagram showing a general circuit constitution of the conventional clock signal generating device 50. The clock signal generating device 50 includes a D-flip-flop (Delayed Flip Flop (Delayed FF) 101. In addition, the clock signal generating device 50 includes a master clock signal input terminal 91 and two output terminals 12 and 13. The master clock signal input terminal 91 is connected to a clock input terminal of the Delayed Flip Flop 101. A non-inversion output signal terminal (Q) of the Delayed Flip Flop 101 is connected to the output terminal 12. In addition, an inversion output terminal (NQ) of the Delayed Flip Flop 101 is connected to the output terminal 13 and to a D input terminal as a feedback. Two clock signals divided from a master clock signal and having substantially phase difference of 180° are outputted from the two output terminals 12 and 13. Note that according to the A/D converter having the interleaved constitution in which the A/D converters of both A/B channels are processed in parallel in the time-division manner, the two clock signals outputted are inputted to an A channel-side sampling clock signal output terminal and a B channel-side sampling clock signal output terminal.
FIGS. 7A to 7C show waveform charts at each part of the conventional clock signal generating device 50 shown in FIG. 6. Referring to FIGS. 7A to 7C, FIG. 7A shows a waveform of the master clock signal (MCLK), FIG. 7B shows a waveform [CLK_A] of the non-inversion output (Q) of the Delayed Flip Flop 101, and FIG. 7C shows a waveform [CLK_B] of the inversion output (NQ) of the Delayed Flip Flop 101.
Next, the operation of the clock signal generating device 50 will be described with reference to FIGS. 7A to 7C.
(a) First, when the master clock signal comes to fall at time t1, as shown in FIG. 7A, it is assumed that the Q output is high and the NQ output is low just before the time t1. In this case, according to the Delayed Flip Flop 101, after the signal falls, Q output timing (tQ) comes after a lapse of Δt from the time t1. Thus, the Q output is switched from high to low after a lapse of Δt from the time t1. Meanwhile, NQ output timing (tNQ) comes after a lapse of (Δt+Δtd) from the time t1. That is, the NQ output is later than the Q output by Δtd. Thus, the NQ output is switched from low to high after a lapse of (Δt+Δtd) from the time t1.
(b) In addition, when the master clock signal comes to fall at time t2, in the case where the Q output is low and the NQ output is high just before the time t2, the Q output is switched from low to high after a lapse of Δt from the time t2 and NQ output is switched from high to low after a lapse of (Δt+Δtd) from the time t2.
As described above, the two clock signals divided from the master clock signal and having the phase difference of about 180° are inputted to the Q output 12 and the NQ output 13 by the operation of the Delayed Flip Flop 101.
According to the clock signal generating device 50 in the conventional example, the NQ output signal of the Delayed Flip Flop 101 is fed back to the D input terminal of the Delayed Flip Flop 101. In addition, mutually inverted signals are outputted from the Q output and the NQ output. Thus, according to the clock signal generating device 50, the master clock signal is divided into the two mutually inverted clock signals outputted.
However, the conventional clock signal generating device 50 shown in FIG. 6 and the A/D converter having the interleaved constitution using the above device have the following problem. That is, as shown in FIGS. 7B and 7C, according to the Delayed Flip Flop 101, a delay (Δtd) is generated between the Q output from the non-inversion output terminal (Q) and the NQ output from the inversion output terminal (NQ) because of the inversion. That is, according to the two clock signals outputted from the conventional clock signal generating device 50, their phase difference is not just 180° in a narrow sense and a difference is caused by the delay time Δtd. Therefore, the problem is that a difference in sampling time is caused between both channels in the A/D converter having the interleaved constitution using the above device.
<Sampling Point Difference Between Both Channels>
The problem in the A/D converter having the interleaved constitution using the conventional clock signal generating device 50 will be described.
When it is assumed that as the two clock signals, an A channel-side sampling clock signal [CLK_A] and a B channel-side sampling clock signal [CLK_B] are inputted to the A/D converter having the interleaved constitution in which the A/D converts of both channels are processed in parallel in the time-division manner, the delay Δtd is generated between a rising edge of the A channel-side sampling clock signal [CLK_A] and a falling edge of the B channel-side sampling clock signal [CLK_B]. Since this delay Δtd causes that the sampling point of the inputted analog signal does not coincide with an ideal point on each of the A channel side and B channel side, the characteristics of the A/D converter is degraded.
FIGS. 8A to 8D are timing charts showing the relation between the analog input signal and sampling timing in the A/D converter. Referring to FIGS. 8A to 8D, FIG. 8A shows an analog input signal waveform, FIG. 8B shows a master clock signal waveform, FIG. 8C shows an A channel-side sampling clock signal [CLK_A] waveform, and FIG. 8D shows a B channel-side sampling clock signal [CLK_B] waveform. In FIGS. 8A to 8D, the falling edge of each sampling clock is set to the sampling point.
In an ideal case, according to the sampling of the inputted analog signal, A channel-side sampling is performed at the falling edge of the CLK_A (FIG. 8A: ●) and B channel-side sampling is performed at the falling edge of the CLK_B (FIG. 8A: ▴) alternately. In this case, the sampling points of both A/B channels are provided at the same interval with respect to the analog signal inputted as shown by ● and ▴ in FIG. 8A.
However, when the conventional clock signal generating device 50 is used, the delay Δtd is generated between the Q output and NQ output of the Delayed Flip Flop due to inversion. Therefore, the delay Δtd is generated between the rising edge of the CLK_A and the falling edge of the CLK_B and between the falling edge of the CLK_A and the rising edge of the CLK_B. As a result, the sampling points of the A/B channels are not provided at the equal intervals as shown by ● and ◯ in FIG. 8A, and an analog signal level off the ideal sampling point is sampled. Thus, the analog-digital conversion precision is degraded due to an error caused by the difference in sampling time between the A channel and the B channel.
In this background, there is a strong demand for a clock signal generating device capable of outputting two mutually inverted clock signals having phase differences of just 180°, to improve analog-digital conversion precision without causing a difference in sampling timing between both channels and without being affected by an error between both channels.